LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux IS
	PORT
	(
		a		: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel		: IN 	STD_LOGIC_VECTOR(1 downto 0);
		b,c,d,e	: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
END mux;

ARCHITECTURE arch_mux OF mux IS
	
BEGIN
	process(a,sel)
	begin
		case sel is
			when "00" =>
				b <= a;
			when "01" =>
				c <= a;
			when "10" =>
				d <= a;
			when "11" =>
				e <= a;
			when others =>
				--
		end case;
	end process;
END arch_mux;